The present invention relates generally to high frequency digital communications test equipment, and more particularly, to phase locked loop circuits therein.
In order to test and measure the quality of signals in equipment at high speed rates, it is necessary to detect and hold that data signal. Generally, phase locked loop circuits used for this purpose have a phase detector to compare the phase of input data signals to the phase of reference signals generated by a voltage controlled oscillator. The difference between these two signals is used to generate an error signal which is fed back to the voltage controlled oscillator through a loop filter so as to control the frequency of its signal output in a direction that reduces this phase difference. Phase locked loops are also known to include a frequency detector having inputs from the data signal and the reference signal and also providing a control signal to the voltage controlled oscillator (VCO) as a function of the frequency difference between these two input signals. When used in combination with the phase detector, the frequency detector provides a rough tuning of the phase locked loop and the phase detector provides a fine tuning. FIG. 1 shows a block diagram of such a phase locked loop having a frequency detector to aid in signal acquisition.
Conventional loop filters typically need to provide for integration and proportionality of input signals thereto. Active circuit elements, such as operational amplifiers, are known to provide sufficient integration of such signals and are commonly employed in loop filters. Unfortunately, with the high frequency input signals, loop filters having active elements in the control path between the phase comparator and the VCO suffer from poor proportionality control: these active elements cause a flat response bandwidth roll off. Passive proportionality filters are known which include passive integrating means, usually capacitors, but this integration has a small dynamic range.
FIG. 2 shows a schematic diagram for a typical non-inverting loop filter for second order phase locked loops (PLL), such as shown in FIG. 1. Operational amplifier 20 has an input signal voltage V.sub.1 connected at its positive input across resistor 12 of R.sub.1 value. V.sub.1 is also connected to ground, or a fixed reference voltage, through capacitor 14 of C value and resistor 16. The negative input to operational amplifier 20 is connected to ground, or a fixed reference voltage, through resistor 18 of R.sub.1 value and also connected to a negative feedback loop having capacitor 22 of C value in series with resistor 24 of R.sub.2 value. If V.sub.1 was connected to the negative input of operational amplifier 20 and the positive input connected to the feedback loop and ground, loop filter 20 would be an inverting loop filter, but with no loss of generality with respect to the discussion below. Loop filter 20 takes the output signal V.sub.1 produced by the phase comparator or the sum of the output signal voltages produced by the frequency comparator and the phase comparator and integrates that signal or sum and provides control in an output voltage V.sub.4, which is the control voltage to the VCO to reset it at the proper frequency. Resistor 24 in series with capacitor 22 in the negative feedback loop provides proportional control over a range of input signal frequencies.
However, because resistor 24 is in the negative feedback loop of operational amplifier 20, the flat response bandwidth suffers a roll-off above the unity gain frequency of the operational amplifier, as shown in FIG. 3. This unity gain frequency is about 1 MHz for most inexpensive op amps. While these conventional circuit elements may perform satisfactorily at low frequency environments, in high frequency phase locked loops a proportionally greater bandwidth is usually desirable. Thus, it would be desirable in such high frequency circuits to eliminate this roll-off of the flat response caused by the operational amplifier since it limits the phase lock loop bandwidth.
FIG. 4 shows a schematic diagram for a conventional phase comparator suitable for use in the PLL of FIG. 1. Exclusive OR gate 46 receives input data signals from data transmission line 40 and data delay line 42. Thus, incoming signals are compared with the delayed version of themselves to produce a signal B output from exclusive OR gate 46. Signal B and reference clock signals produced by the VCO and input by transmission line 44 are inputs to exclusive OR gate 48, which produces an output signal voltage V.sub.1. If the clock signal and signal B are 90 degrees out of phase, the average output signal from exclusive OR gate 48 is 0. As the phase of the clock signal advances relative to signal B, the average output signal from this exclusive OR gate becomes positive. As the clock signal is delayed, the average output signal becomes negative. Again this conventional circuit performs well at low frequencies of input signals, but experiences problems when input data signals have high frequencies. While the VCO has a high Q circuit and, thus, can easily produce narrow clocking pulses, signal B, produced by exclusive OR gate 46, is more difficult to produce as it is as narrow as the clock pulses. Since signal B has gaps without pulses from time to time, it must be generated by logic means and without resonant circuits. For example, at 432 MHz, the pulses of signal B must be 1.2 nanoseconds wide, and the highest speed logic means available commercially today can only produce these pulse widths marginally. Furthermore, since conventional phase detectors for PLLs employ discrete exclusive OR elements, injection noises and parasitic capacitances are present which limit performance at high frequencies.
When acquiring lock, a phase locked loop often needs to act like a frequency comparator. It can do this with a phase comparator for frequency differences up to about 10 times the loop bandwidth. For narrow bandwidth loops, this may not be sufficient. To achieve satisfactory jitter performance, the bandwidth should be sufficiently narrow, compared with the bit rate of the incoming data signals, but this provides a correspondingly narrow pulled-in range. In an attempt to solve this problem, prior PLLs have included frequency comparators to help the PLL acquire lock. One such frequency comparator is a "quadracorrelator". However, quadracorrelators require a broad band 90 degree phase shift in these high frequency environments. One attempt to solve this problem is shown in U.S. Pat. No. 4,015,083 to Bellisio, wherein signal transitions are turned into narrow pulses by differentiating. Again, however, at high frequencies the narrow pulses become a problem to generate.
FIG. 5 shows another frequency comparator for phase locked loops found in the prior art. Digital input data signals from transmission line 40 are compared with VCO-generated reference clock signals from line 44 and delayed clock signals 45 in flip-flops 52, 54, 56, and 58. Flip-flops 52 and 54 output signals corresponding to the present frequency comparison, while flip-flops 56 and 58 output signals corresponding to previous frequency comparisons. Each of these flip-flops inputs a signal to combinational circuit 60, which produces an output signal V.sub.5. This combinational circuit may be designed so that for example, a positive pulse is produced for every cycle slip of phase when the data signal frequency is greater than the reference signal frequency from the VCO and a negative pulse is produced for every cycle slip of phase when the reference signal frequency from the VCO is greater than the input data signal frequency. The negative and positive pulses are then averaged in order to produce final frequency error voltage at the output of the frequency comparator. However, for high frequency environments, this frequency comparator experiences significant problems. At high frequencies, input waveforms have significant jitter and distortion which, at small frequency differences between the data and reference signals, prevent a definitive control pulse from being generated: waveforms may be in phase at some points but not at others over the entire length of the wave. Thus, logic becomes analog, i.e., there are no clear "1"s and "0"s. The phase and frequency relationship jitters at the zero crossing so much that many alternate positive and negative pulses are generated during a cycle slip. The fact that the number of positive pulses exceeds by one the number of negative pulses (when the data signal frequency is greater than the reference signal frequency) may be buried when the average is taken. This results in a significant offset in the transfer characteristic of the frequency comparator in high-frequency applications.
For PLL circuits to properly recover a clock from high-speed data (300 Mb/s and above), each of the problems discussed--with the loop filter, with the phase comparator, and with the frequency comparator--must be solved.